DC25_PAPER_Track07_SolvingAKeySignalIntegrity_Liu_V2.pdf

1、 Solving a Key Signal Integrity Bottleneck Issue to Continue Scaling PCIe 7.0 over Copper Channels Mo Liu,Ph.D Carolina Garcia Robles,Intel Corporation Kai Xiao,Intel Corporation Kuan-Yu Chen,Intel Corporation kuan- Abstract To enable PCIe 7.0 interconnect solutions over copper channels,it is essent

2、ial to comprehensively optimize all link components to meet the electrical requirements specified in the standard.PCB vias are a critical component of interconnects,and at the same time a well-known source of crosstalk and reflection.In this paper,we will focus on one of the key signal integrity bot

3、tlenecks,PCB via stack and array optimization,especially in the IC pinfield area,to improve both reflections and crosstalk.Techniques such as reducing residual stub length,implementing smaller via stacks,and adjusting trace geometries are thoroughly analyzed.The findings indicate that thinner trace

4、geometries and smaller via stack geometries are crucial for minimizing pin field crosstalk and improving impedance tuning.Additionally,the study highlights the importance of early engagement with PCB vendors to understand their capabilities,capacities,and costs,facilitating realistic planning and pr

5、ioritization of enabling work for high-volume manufacturing.Authors Biography Mo Liu has worked as a Sr.Staff Signal Integrity Engineer and a technical lead at Intel.She led the PCIe interface designs and signal integrity analyses on Intel Xeon platforms for the past generations.She received her Ph.

6、D.degree in Electrical Engineering from the University of Notre Dame in 2006 before joining Intel.Carolina Garcia Robles is a signal integrity engineer in the Intel Data Center and AI group.She is involved in modeling and analysis of high-speed differential signaling channels.Carolina joined Intel i