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DC25_PAPER_Track14_DeepReinforcementLearningBasedDesign_Ryu.pdf

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1、 Information Classification:General Deep Reinforcement Learning Based Design Optimization of Power/Ground Ball Map in BGA Package in 3D-ICs Considering Multiple Power Domain Environments Seunghun Ryu,KAIST ysh0067kaist.ac.kr Dongryul Park,KAIST Seonghi Lee,KAIST Hyunwoong Kim,Samsung Electronics San

2、guk Lee,KAIST Hyunwoo Kim,KAIST Seongho Woo,KAIST Changmin Lee,KAIST Jaewon Rhee,KAIST Seokbeom Yong,Samsung Electronics Sangsub Song,Samsung Electronics Jiseong Kim,KAIST Seungyoung Ahn,KAIST Information Classification:General Abstract This paper proposes a deep reinforcement learning(DRL)approach

3、to optimize power/ground ball map design in 3D-IC ball grid array(BGA)packages with multiple power domains(MPD).The proposed method addresses challenges such as power noise and diverse power densities by using a U-net-based DRL algorithm that mitigates simultaneous switching noise(SSN)while optimizi

4、ng the power/ground ball map.The U-net preserves both semantic and spatial information,making the method effective for complex MPD designs.It is scalable and reusable,performing well with different ball map sizes and current source positions.Compared to conventional optimization algorithm such as ra

5、ndom search(RS)and genetic algorithms(GA),the proposed method shows superior optimality performance and lower execution time.Author(s)Biography Seunghun Ryu received his B.S.from Koreatech in 2020 and M.S.from Cho Chun Shik Graduate School of Mobility,Korea Advanced Institute of Science and Technolo

6、gy(KAIST)in 2022,where he is currently pursuing a Ph.D.In 2022,he was a visiting scholar at Missouri University of Science and Technology.His research interests include high-speed interconnection design and machine-learning-based power integrity(PI)design for 2.5D/3D ICs.Dongryul Park received his B

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1. **研究目标**:提出基于深度强化学习(DRL)的3D-IC BGA封装电源/地球映射优化方法,解决多电源域(MPD)环境下的电源噪声(SSN)问题。 2. **核心方法**:采用U-Net结合A2C算法,通过分析SSN的解析模型(含寄生参数矩阵)作为奖励函数,优化球体布局以降低SSN。 3. **性能对比**:与传统算法(随机搜索RS、遗传算法GA)相比,DRL在SSN抑制上更优(如15×15区域SSN降低13.00 vs. GA的13.00),且执行时间更短(6.3秒 vs. GA的15274秒)。 4. **关键优势**:方法具备可扩展性(支持7×7至15×15区域)和可重用性(适应不同电流源中心CSC布局),同时遵循电源球按域分组的实际设计规则。
**DRL如何优化BGA?** **3D-IC的SSN难题?** **U-网在DRL中的作用?**
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