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DC25_PAPER_Track06_EnhancedApplicationofHigh-SpeedFlexibleMaterialsintheArchitecture_shen_v2.pdf

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1、 Information Classification:General Enhanced Application of High-Speed Flexible Materials in the Architecture Design of Network Core Equipment Dayong Shen Bytedance Jian Yang Ruijie Networks Chuansheng Cheng Bytedance Luoyi Fang Bytedance Feng Luo Bytedance Anbing Sun Ruijie Networks Jianwei Yu Broa

2、dcom I Lu Xiao Shengyi Electronics Guang Yuan Zhu Shengyi Electronics Yang Liu Shengyi Technology Chiji Guan Shengyi Technology Information Classification:General Abstract With the rapid development of network communication technology,the Serializer/Deserializer rate has developed from 25G to 112/22

3、4G.Driven by AIGC,the network hardware development speed is still accelerating.High speed,large capacity,and high power consumption make the design of the hardware system more and more complex,and the hardware architecture design of communication equipment has become more and more critical.At presen

4、t,the common architectures of cassette core switches include the traditional single PCB solution,the Mezzanine Connector solution,the Cable solution and the vertical mainboard architecture.Each architecture has its own characteristics.With the advent of the next-generation 100T switching chip,whethe

5、r the existing architectures can withstand the challenges of SI and heat dissipation design requires the joint efforts of system engineers.In addition,the breakthrough of innovative architecture solutions is also the goal that everyone pursues.This paper will utilize high-speed flexible materials an

6、d design several enhanced technical solution equipment architectures based on the existing architectures in the industry to achieve the optimal combination of high-speed SI performance and heat dissipation design.The key contents include the analysis of mainstream cassette switch architectures,the p

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1. **背景与挑战**:网络核心交换机速率从25G发展到112/224G,AIGC驱动硬件加速,高带宽、高功耗带来SI(信号完整性)和散热设计挑战。 2. **传统架构局限**:传统单PCB、Mezzanine Connector、Cable及垂直主板架构在下一代100T芯片(如1024对112G或512对224G SerDes)下面临端口密度、信号损耗等问题。 3. **创新方案**:采用**刚柔结合板(Rigid-Flex PCB)**,通过PTFE材料(低损耗)优化设计,提出三种增强架构(水平主板/水平HSIO、垂直主板/水平HSIO、水平主板/垂直HSIO),仿真显示112G速率下通道插入损耗≤21.72dB(符合IEEE标准)。 4. **验证与未来**:测试板验证了6-18英寸链路性能,未来需解决阻抗匹配、多层钻孔可靠性等问题。
**高速材料应用?** **核心架构挑战?** **散热与SI设计?**
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