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DC25_PAPER_TRACK01_UsingResponseSurfaceMethodology_Neally_v2.pdf

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1、 Using Response Surface Methodology to Overcome Incumbent Inertia:A T-coil Case Study Scotty Neally,AMD,Inc.Scotty.N David Kopp,AMD,Inc.David.K Garth Sundberg,Ansys,Inc.Garth.S Abstract The most common layout optimization technique is to iterate upon frequency domain performance until a criterion is

2、 met.We believe this results in either a sub-optimal or over-constrained solution due to a few critical interactions.Frequency domain metrics do not comprehend risetime degradation and neglect system-level equalization,while iteration can exclude viable solution space as the design progression intro

3、duces new boundary conditions.Early electrical decisions like pin assignment,circuit topology,and stackup ordering have an outsized influence on the signal and power integrity.By down-selecting,subject matter experts choose to reduce the design space in favor of computational expediency,but this may

4、 unintentionally bias the solution space for later milestones.Unfortunately,as the design matures,teams often lack time or resources to revisit these early decisions which now limit the design.In this paper,we call this tendency incumbent inertia:the hesitancy to deviate from an established norm due

5、 to sunk costs.Our case study will consider a fixed area coil that aims to maximize eye size at 12Gbps for channels in both read and write directions while considering ESD loading at a single termination value.Previously,this process would require significant time and resources to complete,but it ca

6、n now be expedited using AI-aware tools to explore unique and previously unconsidered design corners with little overhead compared to traditional methods.Author Biographies Scotty Neally received a B.S.E.E from California Polytechnic University,San Luis Obispo.He is an accomplished signal integrity

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1. **问题提出**:传统布局优化依赖频域迭代,易导致次优或过约束解,因早期电气决策(如引脚分配、电路拓扑)受“ incumbents inertia”(既得利益惯性)影响,限制设计空间。 2. **方法创新**:结合AI工具(Ansys optiSLangAI)、响应面法(RSM)和高性能计算(HPC),直接以时域眼图指标(眼高、眼宽)为优化目标,减少频域与时域性能差异。 3. **关键发现**:T-coil设计中,AP层和Mx层的匝数(dev_1_turns、dev_2_turns)对眼图影响最大,但读/写方向眼高存在权衡(Pareto前沿);总电感/电阻与时域性能相关性低。 4. **计算效率**:不同设计里程碑(如Prelayout至signOff)的仿真资源需求差异显著,需并行计算优化(如80核RaptorX)。 5. **未来方向**:扩展多数据率、多通道优化,结合ESD负载和制造公差分析,推动AI驱动设计流程革新。
**AI如何优化设计?** **T-coil设计瓶颈?** **设计惯性如何破局?**
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