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DC25_PAPER_Track10_NovelMultiPowerDomainPCB_Manoharan_v2.pdf

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1、 Information Classification:General DesignCon 2025 Novel Multi Power Domain PCB Decap Layout Synthesis using Multi-Agent Reinforcement Learning Haran Manoharan,Missouri S&T hm6h6mst.edu Hanfeng Wang,Google Jingnan Pan,Google Xu Gao,Google Kelvin Qiu,Google Chulsoon Hwang,Missouri S&T Information Cla

2、ssification:General Abstract Modern Systems on Chips(SoC)have more than one power domain for efficient power management across multiple functional blocks.In the design of Printed Circuit Board(PCB)pre-layout stage,engineers use physical insight and trial and error methods to place decaps to satisfy

3、the target specifications needed for the SoC for efficient operation in the PCB.This is a time-consuming and ineffective method since there could be numerous possibilities.This could sometimes lead to overdesign or under-design for some power domains;repetitive iterations are required to overcome th

4、is challenge.This paper addresses a challenge not tackled at this scale beforespecifically,managing multiple power domains in a practical setting.For the first time,we proposed a hybrid algorithm that combines multi-agent reinforcement learning with a genetic algorithm to effectively handle the comp

5、lexity of decap pre-layout synthesis for multiple power domains.This work optimizes the placement,orientation,value,and number of decaps,offering a solution that accounts for the intricate dependencies and constraints inherent in PCB pre-layout designs,where no initial layout is available to begin t

6、he optimization process.This algorithm computes the PDN impedance using an in-house tool making it fast and completely free of other commercial simulation tools.The algorithm has been designed in a way to take inputs directly from a board file or with just ball map and PCB stackup information making

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1. **研究目标**:提出基于多智能体强化学习(MARL)与遗传算法(GA)的混合算法,优化多电源域PCB去耦电容(decap)预布局设计,解决传统试错法效率低、易过设计/欠设计的问题。 2. **核心方法**: - 每个电源通孔作为独立智能体,采用无状态Q-learning,通过中央控制器协调动作与奖励分配。 - 结合GA优化decap数量、值及布局,确保满足各电源域目标阻抗(如移动SoC的36个电源域)。 3. **验证结果**: - 算法在30分钟内为36电源域移动SoC生成无重叠的decap布局(初始265端口→优化至87端口),满足所有93项阻抗目标。 - 简单测试案例(4电源域)5分钟内完成,阻抗曲线达标(如8.7mΩ@25MHz)。 4. **优势**:无需商业仿真工具,直接输入PCB文件或球栅映射与堆叠信息,支持自动化集成。
**多域优化难题?** **智能布局如何实现?** **30分钟搞定36域?**
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