DC25_PAPER_TRACK10_BalancingCurrentDensityToHigh_Hostetler.pdf

1、 1 Balancing Current Density to High-Power ASICs in Lateral Power Delivery Designs Brian Hostetler,HPE Inc.2 Abstract Increased power consumption of todays CPUs,GPUs,and ASICs presents new problems for PCB designs that employ traditional lateral power delivery.One problem is the significant I2R loss

2、 in the copper power planes.Another major concern is current imbalance between power vias.This can lead to overheated and failed vias in addition to a risk of electromigration problems in the solder bumps and/or solder balls.This paper describes the technique of using variable via diameters within t

3、he power via field.This alters the conductivity of each individual via and also impacts the leftover webbing in the power planes made by the antipads.The paper analyzes the effectiveness of this approach to a new PCB design,discussing initial simulation results along with measurements of via current

4、 uniformity on the manufactured board with ASIC attached.Author(s)Biography Brian Hostetler is a senior electrical engineer at Hewlett Packard Enterprise,specializing in power integrity.He is responsible for the design of power delivery networks for Cray supercomputer systems.He develops cabinet-lev

5、el and board-level designs,simulations,and measurements.He is also responsible for the design and verification of ultra-low jitter clock solutions for next-generation ASICs.He holds degrees from Indiana State University and Purdue University.3 Motivation Application-specific integrated circuits(ASIC

6、s)have power demands that are increasing faster than their physical size,resulting in a continuous growth of their power density.Current density in the power distribution network is likewise increasing without corresponding improvements in PCB technology.Copper plating thicknesses within via barrels