先进封装互连综合中偏移通孔和泪滴的认识.pdf

1、On Awareness of Offset-Via and Teardrop in Advanced PackagingInterconnect SynthesisAuthor:Hao-Ju Chang,Yu-Hung Chen,Hao-Wei Huang,Yihua Yeh,Hung-Ming Chen,Chien-Nan Jimmy LiuNational Yang Ming Chiao Tung UniversitySpeaker:Hao-Ju ChangOutlineIntroductionOptimizing Offset-via AssignmentS-route Guided

2、A*SearchExperimental ResultConclusion2IntroductionBackground and MotivationThe area of single chips has continuously increasedWhile this has boosted performance,it has also led to a decrease in manufacturing yieldChiplet technology has become mainstreamConnect different chiplets through fine-pitch R

3、edistribution Layer(RDL)connectionsChallenges of Advance PackageOffset-vias and teardrops enhance reliability and manufacturabilitySignal integrity(SI)issues need to be addressed3Die1Die2Package SubstrateMicro bumpC4 bumpRDLsOffset-Via and TeardropTraditional stack-via suffers more line strainEspeci

4、ally when the number of RDL layers is increasedOffset-Via improves the reliabilityTwo adjacent layers cannot have vias in the same positionTeardropConnecting wires directly to vias can also lead to high stress and cracksEmploying metal shrinkage from the via to the wire can alleviate stressIncorpora

5、ting offset-via and teardrop structures in die-to-die routing 1Helps reliability Significantly reduces the routing resources1 H.-M.Chen,C.-W.Ho,S.-H.Wu,W.Lu,P.-T.Huang,H.-J.Chang,and C.-N.J.Liu,“Reshaping system design in 3d integration:Perspectives and challenges,”in Proceedingsof the 2023 Internat

6、ional Symposium on Physical Design,pp.7177,2023.4Signal IntegritySignal integrity(SI)becomes a more serious issueEye Diagram is a typical way to evaluate SIEye Width(EW)increase:Lowering the likelihood of timing errorsLarger Eye Height(EH)Reducing the possibility of functional errorsAnalyze the SI p