陈桂芳-2.5D IC硅中介层电源完整性和可靠性分析中的签核挑战和解决方案.pdf

1、Confidential 2018 Enflame TechSign-off Challenges and Solutions in Power Integrity and Reliability Analysis of 2.5DIC Silicon InterposerFirst Author:Jiajun Zhao(Enflame)Co-Second Author:GuifangChen(Enflame),Xiaodong Wang(Ansys),Yiting Lin(Ansys),Yuming Sun(Enflame),Pengyue Yin(Enflame)Jan 2025Confid

2、ential 2018 Enflame TechChallenges of Power Integrity and Reliability Analysis for Silicon InterposerDifficulty for Analysis:1.Power integrity co-simulation with multiple dies in 2.5D COWOS structure.2.How to cover comprehensive interposer power integrity and reliability analysis flow:Connectivity r

3、obustness for supper large pin numbers.PG grid optimization to meet interposer design performance.Interposer reliability requirements.3.Too late to optimize interposer design after SOC data ready.Interposer with 300000+micro bump and 44000+copper pillarComplex interposer layout design with 5 metal l

4、ayers and DTC to achieve good performanceConfidential 2018 Enflame TechPower Integrity and Reliability Analysis methodology for Silicon InterposerinterposerChip interfacePackage interfaceChip interface bumps as probesPackage ploc bumpsPDN quality checks for chips with multiple interfaces.Create pack

5、age bumps on one interface and probe sources on micro bumps.Probe sources can be constant or PWL sources.Perform a static/dynamic analysis for checking layer drop,PG grid robustness.Perform power EM analysis based on static/dynamic simulation results.Interposer are being signed off separately for th

6、e ESD.Conquer zap simulations between micro bump and C4 bump.Check the Arc resistance and current density on ESD discharge path.Find all the connection points which are expected to connect to the DIE and create probes on that locationPlace constant or PWL current sources at the probes.Perform static