DC25_SLIDES_Track07_InvestigationOfPinFieldCrosstalk_Luoh_V2.pdf

1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025 Information Classification:GeneralInvestigation of Pin Field Crosstalk Degradation due to PCB Manufacturing VariationAmy Luoh,(Intel)Amy Luoh(Intel),Xiaoning Ye(Intel),Vijay Ku

2、nda(Intel),Chenghai Yan(Intel),Kuan-Yu Chen(Intel)2Information Classification:GeneralSPEAKERSAmy LuohTech Lead,IAmy Luoh is currently a Technical Lead at Intel Corporation.She received the B.S.and M.S.degree in electrical and computer engineering from Oregon State University.She has been working as

3、a signal integrity engineer in server group at Intel since 2005.She leads test board designs,performs routing reviews,PCB material studies and signal integrity and power integrity related simulations and measurements for the server board designs.3Information Classification:GeneralAuthorsVijay KundaS

4、ignal Integrity Engineer,IVijay Kunda works as Signal Integrity Engineer within DCAI Intel Corporation.Vijays primary focus is to lead,simulate,review platforms with an emphasis on high speed and low speed designs.He is also involved in a lot of pathfinding work such as loss/crosstalk analysis and o

5、ptimized stack-ups.Prior to Intel,Vijay was with Oracle for over 10 years specializing in high speed pre and post layout full board DDR2/3/4 simulations and high-speed serial interconnects simulations.He received his MS in Electrical Engineering from the University of South Carolina specializing in

6、Antenna Design.Xiaoning YeSr.Principial Engineer,IXiaoning Ye is currently a Sr.Principal Engineer at Intel Corporation,working on signal integrity of high-speed interconnects in Server systems.He received his Bachelor and Masters degrees in electronics engineering from Tsinghua University,Beijing,C