DC25_SLIDES_Keynote_TheTransformativePowerOfAccelerated_Linford.pdf

1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025 The Transformative Power of Accelerated Computing and AIJohn Linford,Ph.D.|Lead Technical Product Manager CAE2One Year Rhythm|Supercluster Scale|Full-Stack|CUDA EverywhereNVIDI

2、A BUILDS AI SUPERCOMPUTING INFRASTRUCTUREGrace BlackwellMGX NodeNVLink SwitchQuantum SwitchSpectrum-X SwitchChips Purpose-Built for AI SupercomputingGPU|CPU|DPU|NIC|NVLink Switch|IB Switch|ENET SwitchCUDA DOCA NCCLCluster-Scale SoftwareSystem SoftwareChip SoftwareCUDA-X LibrariesNIMCUDA-AcceleratedA

3、gentic AI LibrariesOmniverseCUDA-AcceleratedPhysical AI LibrariesAccelerated Software StackGB200 NVL72 SuperPODGENERATIVE AI MOMENTUM IN SEMICONDUCTOR MANUFACTURINGCode&Language Translation Architecture Search Verilog Code Generation P&R,Verification,DRC,.AgentEngineering Copilot Engineer Training F

4、ield Service Fab OperationsAgentic Workflow Quality Control Yield Improvement Process OptimizationNVIDIA BUILDS AI TO BUILD CHIPS FOR AI202420192020202120222023HPGCN(Testability)PRIMAL(Power)PowerNet(IR Drop)ParaGraph(Parasitics)GRANNITE(Switching Activity)MAVIREC(IR Drop)DOINN(Lithography)DesignAna

5、lysisChipNeMo(Engineering)VerilogEval(RTL)RTLFixer(RTL)ClusteringAgent(Cell)VerilogCoder(RTL)DesignAssistanceFVAgent(FV)FVEval(FV)OPCAgent(Lithography)FIST(PD)NVCell-RL(Cell)ParaSize(Analog)AutoCRAFT RL(Analog)AutoDMP(PD)DesignOptimization(RL,BO)Graph Cluster(PD)PrefixRL(Synthesis)Transsizer(PD)TAG(

6、Analog)BufFormer(PD)ILILT(Lithography)Dream-GAN(PD)Clustering(Cell)DesignOptimization(Gen AI)VAESA(Arch)BUILDING AN LLM FOR CHIP DESIGNM.Liu et al,ChipNeMoC.-T.Ho et al,VerilogCoderParameter TrainingRetrieval Augmented Generation(RAG)In-Context LearningAgentEXPLOSION OF LLM APPLICATIONS FOR CHIP DES