DC25_PAPER_Track07_NextGen224GbpsChiptoChipMR_Wu_V2.pdf

1、 1 Next Generation 224 Gbps-PAM4 Chip-to-Chip/MR SERDES,Package,Channels,and Link Simulation and Analysis Hsinho Wu,Intel Mike Li,Intel Masashi Shimanouchi,Intel Itamar Levin Ariel Cohen 2 Abstract In our previous DesignCon papers,we studied 224 Gbps-PAM4 links for long-reach(CR/KR/LR)applications t

2、argeting the upcoming IEEE 802.3dj and OIF-CIE-224G-PAM4 standards.This paper focuses on 224 Gbps-PAM4 chip-to-chip(C2C)and medium-reach(MR)links,which play critical roles in systems targeting applications such as telecom,data converters,and AI/ML.C2C/MR links need to achieve delicate balances among

3、 error rate performance,latency,and power consumption due to their intended applications,interconnect density,and physical constraints such as power and thermal limitations.We will advance our link simulation and analysis for 224 Gbps-PAM4 C2C/MR with the following forward motions:1.Comprehend the i

4、ndustrys 224 Gbps-PAM4 C2C/MR requirements and trade-offs.2.Use the latest C2C/MR channels(130)with insertion loss(IL)between 4-30 dB and MR package configurations.3.Comprehend the latest trending reference packages and reference transmitter/receiver and rationale behind.4.Study C2C/MR FEC options a

5、nd performance.End-to-end waveform-domain bit-by-bit simulations and statistical COM analysis will be conducted to determine the solution space and performance of C2C/MR links.The implications of this comprehensive investigation and its outcomes on the development of the IEEE 802.3dj C2C and OIF-CEI

6、-224G-MR-PAM4 specifications will be discussed.3 Author(s)Biography Dr.Hsinho Wu is a Principal Engineer at Altera Corporation.He presently works on high-speed communication systems IPs.His development and research interests include signal integrity,clock and data recovery,equalizations,device and s