AI或HPC芯片功耗优化新方法：工作负载感知的自适应电压调节.pdf

1、Andrea Matteucci,Senior Product ManagerNovel Power Optimization Methods for AI/HPC Chips:Workload-Aware Adaptive Voltage ScalingEnergy consumption surge Environmental concernsTechnological trade-offs Performance limitations Thermal management complexities Reliability issuesPower Consumption Becomes

2、a Critical LimiterIndustry best practices rely on:Power-efficient design methodologiesWorst-case adaptive power/performance scalingIntegration of advanced cooling technologiesThe POV of the silicon device architect:highest Performance at lowest Power for the devices lifePerformance:typically defined

3、 by specification goals.Target frequency.Power Consumption:defined by the minimum operating voltage.It is searched in characterization:time/cost demanding.Reliability:functionality must be granted for the devices life,including all operational conditions.PerformancePowerReliabilityPerformancePowerRe

4、liabilityDynamic methodsDVFS:SW-controlled.F,V adjusted according to application performance requirements or temperature thresholdsAVS:closed-loop method that dynamically adjusts voltage levels according to the current operating conditionsGapsComplex:not all companies will or can implement Still nee

5、d guard bands,leaving performance or power on the tableHow to Save Power?Not all guard bands are needed all the time and at the same timeResult:most of the time“wasting”power when not neededVoltage Guard BandsN ovel approac h that utilizes in-c hip vis ibility to rec laim exc es s guard-bands to s a

6、ve powerproteanTecs Approach to Power ReductionMeet performance spec,at lowest power,ens uring reliabilityGuard-band behavior over timeExcess voltage leads to Excess voltage leads to needless power needless power consumptionconsumptionWhite Paper Application-Specific Power Performance Optimizer Base