Intel_s Ponte Vecchio GPU - Architecture Systems and Software FINAL.pdf

1、Hong Jiang,Ph.D.Chief GPU Compute Architect,Intel FellowIntel CorporationAugust 2022Intel ConfidentialDepartment or Event Name2 2Ponte Vecchio PlatformoneAPISoftware StackPonte Vecchio Architecture HighlightsApplication PerformanceIntel ConfidentialDepartment or Event Name3 3ArchitectureXecorePonte

2、Vecchio 2-StackIntel ConfidentialDepartment or Event Name4 4Ponte Vecchio x4 Subsystem with XeLinks Ponte Vecchio OAM Ponte Vecchio x4 Subsystem with XeLinks +2S Sapphire Rapidsx4 subsystem supports all-to-all connection across XeLinksOAMs support all-to-all topologies for both 4 GPU and 8 GPU platf

3、orms Intel ConfidentialDepartment or Event Name5 5Ponte Vecchio PlatformoneAPISoftware StackPonte Vecchio Architecture HighlightsApplication PerformanceIntel ConfidentialDepartment or Event Name6 6Specification and more information:https:/oneAPI Level ZeroEcosystem HALsSYCL/OpenMP LanguagesEcosystem

4、 LanguagesToolsToolsPort,Compile,Debug,AnalyzeSW Contract:Open,Free,Everywhere,ForeveroneAPI LibrariesEcosystem&Intel LibrariesEcosystem&Intel LibrariesEcosystem Toolsx86 ISAXeGPU ISAFPGA ISAASIC ISAARM ISANV GPUISA(PTX)Intel ConfidentialDepartment or Event Name7 7Host InterfaceLevel-Zero InterfaceO

5、ptimized Middleware&FrameworksCompatibilityToolDirectProgrammingData Parallel C+And other Programming languagesAPI-BasedProgrammingLibrariesTarget System SoftwareTarget System SoftwareTarget System SoftwareTarget System SoftwareOptimized ApplicationsCPUGPUFPGAOther AcceleratorSysmanResource Mgmt Pow

6、er Frequency Temperature HealthThe oneAPILevel-Zero APIs provide a low-level hardware interface to support cross-architecture programmingInterface for oneAPIand other tools to accelerator devicesFine gain control and low latency to accelerator capabilitiesMulti-threaded design For GPUs,ships as a pa