DC25_SLIDES_Track3_DevelopmentOfACo-PackagedApplication_XU_V2.pdf

1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025 Information Classification:GeneralDevelopment of a co-packaged Application Specific IC with direct drive optical engine chipletsQing Xu(Ranovus)Jeff Hutchins,Bin Cao,Omid Jafar

2、i,Georg Roell,Hojjat Salemi,Hamid Arabzadeh(Ranovus Inc.)Chih-Yi Kuan,Yu-Cheng Hsu,Chih-Wei Sung(MediaTek Inc.)Bono Liao,Brad Hsu,Mark Lin(Foxconn Interconnect Technology)2Information Classification:GeneralImageSPEAKERSQing XuSr.Technical Leader of Application Engineering,Ranovus I|Qing Xu holds a B

3、SEE degree from Shanghai Jiao Tong University,a Master Ingnieur degree from ESME Paris,and a Ph.D.in Electrical Engineering from Tlcom Paris(ENST).He joined RANOVUS Inc.in 2017,where he currently serves as Senior Technical Leader of Application Engineering.Qing has also held various roles at Belden

4、and Ericsson.He is the author of over 30 conference and technical papers and holds six granted U.S.patents.His current research focuses on monolithic integrated photonics transceivers,with an emphasis on close integration and co-optimization with high-speed SerDes.3Information Classification:General

5、Development of a co-packaged Application Specific IC with direct drive optical engine chipletsIntroduction to Co-Packaged Optical Engine ChipletsKey Components and CPO System DesignSystem Co-SimulationCPO System Integration and Bring-UpTest Results of the CPO SystemRoadmap for Scaling to 200G Signal

6、ingAgenda4Information Classification:GeneralAI training utilizes large quantities of matrix multiplicationGPUs are designed to accelerate“multiply and add”operations used in AI matrix multiplicationEach row in matrix A is paired with every column in matrix B Lots of computation with lots of paramete