DC25_SLIDES_Track10_HighEfficiencyTimingAwarePower_Xiao_V3.pdf

1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025Information Classification:GeneralHigh-Efficiency Timing-Aware Power Integrity Analysis Methodology for Digital Integrated CircuitsSpeaker:Andrew John Marshall(Huawei Canada)Xia

2、o Xiao(Huawei),Xiaoping Xu(Huawei),Tianyu Liang(Huawei),Wenquan Yang(Huawei),Wenli Zhu(Huawei),Xinwen Bi(Huawei),Siqi Liu(Huawei)2Information Classification:GeneralImageSPEAKERSAndrew John MarshallDistinguished Engineer,Huawei CanadaAndrew.MAndrew Marshall received his Bachelors of Electrical Engine

3、ering Degree,Micro Electronics from Carleton University,Ottawa,Canada in 1993.He has worked in several IC companies in the areas of analog and mixed-signal circuit design and methodology creation.Leadership roles in standard cell library products followed by 25years in high speed serdes designs and

4、implementations of all block types in many leading-edge technologies.He joined Huawei technologies Canada Ltd.in 2011 were leadership in high speed interface product IPs contributed to Huawei systems success in the global ITC industry.As a distinguished engineer he currently leads an analog design e

5、xploration team researching high speed interfaces in Ottawa,Canada.3Information Classification:GeneralAUTHORS4Xiao Xiao is a senior signal and power integrity engineer in Huawei Technologies Co.,Ltd.He is currently focused on researches including the modeling,design,and measurement methodologies of

6、SIPI.He received his master degree in University of Electronic Science and Technology of China.Xiaoping Xu is a hardware systems engineer at Huawei Technologies Co.,Ltd,where he has been working on system-level design of power integrity and signal integrity since 2017.He received masters degree from