DC25_SLIDES_TRACK2_ModelingAndStudyOfNonLinearity_Bhardwaj_V4.pdf

1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025 Information Classification:GeneralModeling and Study of Non-Linearity in Double Data Rate(DDR)Memory LinksKanupriya Bhardwaj,AMD2Information Classification:GeneralImageSPEAKERK

2、anupriya BhardwajSenior Member of Technical Staff,AMDKanupriya.BKanupriya Bhardwaj received the B.Tech.and M.Tech.degrees in Electrical Engineering from IIT Kharagpur,India,in 2007,and Ph.D.from Stanford University in 2013.She has since worked at Intel and Altera and is currently at AMD,working on p

3、erformance modeling of links.3Information Classification:General Motivation DDR Signals and Linearity Metrics Proposed Methodology Characterizing Link Performance Application to LTI based Tools ConclusionOUTLINE4Information Classification:General Server DDR entails multiple parallel,area-optimized l

4、anes Focus has been towards signal integrity(SI)related optimizations Accurate modeling of other channel impairments is also important Studying Non-Linearity(NL)in DDR Links is the goal of this work Feedback to design Realistic Link Margin analysis Improved correlation with Post-SiMOTIVATION55thGen

5、AMD EPYC processorsSource:https:/ Classification:General Swing is entirely dependent on the DB/DRAM supply Ron/Rtt ratio determines the swing and reflections For Ron=Rtt,Vdd=1V o Swing=0.5V o Common Mode Voltage(VCM)of 0.75V DDR SIGNAL VOLTAGE PROFILE6=+=+2 +Information Classification:General Signal

6、 from Tx Driver passes through the physical channel Interacts with the Rx Analog Front End(AFE)where single ended to differential conversion takes placeSIGNAL PATH IN A DDR LINK7AFECTLE=Continuous time Linear EqualizerVGA=Variable Gain AmplifierInformation Classification:General More pronounced redu