DC25_SLIDES_Track10_NovelMultiPowerDomainPCBDecap_Manoharan.pdf

1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025 Information Classification:GeneralNovel Multi Power Domain PCBDecap Layout Synthesis usingMulti-Agent ReinforcementLearningHaran Manoharan(Missouri University of Science&Techno

2、logy)Haran Manoharan(Missouri University of Science&Technology),Hanfeng Wang(Google),Jingnan Pan(Google),Xu Gao(Google),Kelvin Qiu(Google),Chulsoon Hwang(Missouri University of Science&Technology)2Information Classification:GeneralSPEAKERSHaran ManoharanPhD Student,Missouri University of Science&Tec

3、hnologyhm6h6mst.edu|https:/emclab.mst.edu/members/phd-student/haran-manoharan/|Haran Manoharan received the B.S.degree in electronics and communication engineering from Anna University,Chennai,India,in 2020.He is currently working toward the Ph.D.degree in the EMC Laboratory,Missouri University of S

4、cience and Technology,Rolla,MO,USA.He has also worked as a Hardware Ph.D.intern in the High-Speed Optics group at Cisco.His research interests include Power Delivery Network design and optimization,signal integrity and machine learning.3Information Classification:GeneralOutline4 Introduction Propose

5、d Algorithm PDN Impedance Modelling Decap Optimization Genetic Algorithm Validation Cases ConclusionInformation Classification:GeneralIntroduction5 Modern SoCs have multiple power domains to optimize energy efficiency and performance by selectively controlling power to different components and funct

6、ions within the chip.Optimization of both placement and value for all the power domains simultaneously is a challenging task.SoC Pin MapInformation Classification:GeneralGoal6IC pin map and board parametersOptimized decap placement pattern An ML algorithm to automatically design and optimize the PDN