DC25_SLIDES_Track13_PathToPCIeGen7Challenges_Pandankerilshaji.pdf

1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025 Information Classification:GeneralPATH TO PCIE GEN 7.0:CHALLENGES AND DESIGN CONSIDERATIONS FOR NEXT GENERATION INTERNAL CABLINGAshika Pandankeril Shaji,(TE Connectivity)Ashika

2、 Pandankeril Shaji(TE Connectivity),Calvin Feng(TE Connectivity),Nathan Tracy(TE Connectivity)2Information Classification:GeneralAUTHORSAshika Pandankeril Shaji(Speaker)Staff System Architect,TE CAshika has a strong foundation in electrical and computer engineering from her Bachelors and Masters deg

3、rees.With 8 years of experience her technical expertise helps in developing cutting-edge solutions that meet modern technological demands for TE customers.Nathan TracyPrincipal System Architect,TE Connectivity Nathan has more than 30 years of experience in technology development,marketing,and busine

4、ss development for TE in areas including RF/microwave,and high-speed signaling technology for the networking,Nathan is active in several industry standards and associations.3Calvin FengPrincipal System Architect,TE Connectivity Calvin has over 21 years of industry experience in signal integrity and

5、high-speed connector designs.In his role as system architect,he heavily focuses on capturing industry trends and develop future generation solutions,including 112G mezzanine connector and high-speed interconnects for PCIe Gen 7.0.Information Classification:GeneralHigh-Speed Internal Cabling4Internal

6、 Cabling Plays a Significant Role in Compute/Storage Application for PCIe Gen7Requirements/Voices from Compute/Storage ApplicationInformation Classification:GeneralLow-Profile Interconnect Application5OCP DC-MHS ApplicationPCIe AICPCIe Riser CardHost Board(MB)Under PCIe Riser Card Under PCIe AIC App