DC25_PAPER_Track10_HighEfficiencyTimingAwarePower_Xiao_V3.pdf

1、 1 High-Efficiency Timing-Aware Power Integrity Analysis Methodology for Digital Integrated Circuits Xiao Xiao,Huawei Technologies Co.,Ltd Xiaoping Xu,Huawei Technologies Co.,Ltd Tianyu Liang,Huawei Technologies Co.,Ltd Wenquan Yang,Huawei Technologies Co.,Ltd Wenli Zhu,Huawei Technologies Co.,Ltd X

2、inwen Bi,Huawei Technologies Co.,Ltd Siqi Liu,Huawei Technologies Co.,Ltd Abstract The power integrity(PI)analysis methods for current digital circuits design can be categorized into three types,target impedance analysis,transient simulation based on current behavior,and timing analysis combined wit

3、h power supply noise.Compared to the first two methods,timing analysis considers the impact of power supply induced jitter(PSIJ)and avoids pessimistic estimates.However,defining the accurate critical path is very challenging due to high computational complexity and time complexity through netlist tr

4、ansient simulation.In this paper,we introduce an advanced Timing-Aware Power Integrity Analysis(TAPIA)methodology that addresses the computational challenges inherent in defining critical paths for digital circuits.Unlike traditional approaches which often yield conservative estimates,our TAPIA meth

5、od incorporates cell-level jitter performance reconstruction,synergizing extensive data processing with intricate timing analysis to streamline computational demands.Our innovative approach establishes a comprehensive dynamic jitter library at the standard cell level,enabling precise reconstruction

6、of power supply induced jitter sensitivity,duty cycle distortion,and random jitter performance across the entire signal path.This paper delves into the sophisticated algorithmic framework that underpins this reconstruction process.Empirical evaluations confirm that our TAPIA method delivers timing m