DC25_PAPER_Track03_NextGeneration224GbpsPAM4Linear_Li_V2.pdf

1、 1 Next Generation 224 Gbps-PAM4 Linear:Host TX/RX,Electrical/Optical Channel Characteristics,and End-to-End Link Simulation and Analysis Mike Li,Intel Edward Frlan,Semtech Hsinho Wu,Intel Masashi Shimanouchi,Intel Itamar Levin,Intel Ariel Cohen,Intel Mark Kimber,Semtech Bill Kirkland,Semtech 2 Abst

2、ract This paper will focus on comprehensive 224 Gbps-PAM4-Linear electro/optical link investigations.We will start with the recently adopted:1.)CEI-224G-LR-PAM4 1 TX and RX architecture,die AFE and matching circuit network,jitter,noise,and SNR characteristics,equalization capabilities(i.e.,TX FIR,an

3、d RX CTLE+FFE/DFE+MLSD),and reference package for host SERDES.2.)802.3dj adopted 800GAUI-4/1.6TAUI-8 C2M PCB/cable and connector loss and crosstalk characteristics 2.3.)802.3dj adopted 800GBASE-DR4/1.6TBASE-DR8 optical PMDs for TP2 and TP3 optical output and input assumptions 2.Then we conduct the e

4、nd-to-end link simulations and analysis.Design of experiments(DOEs)include:a.)2-D sweeping of host to module input electrical channel insertion loss(IL)(TP1a)and xtalk.b.)sensitivity analysis of end-to-end link performance versus FFE/DFE tap wight and length,as well as versus MLSD tap length and wei

5、ght,will be conducted.Comparisons of those simulations with experimental measurements will be carried out as well.Implications of findings from those leading-edge state of art investigations to the 224Gbps-Linear-PAM4 specification development currently under OIF will be discussed and highlighted.3

6、Author(s)Biography Dr.Peng(Mike)Li is an Altera Fellow and a Chief Technologist for high-speed SERDES,I/O,and interconnects at Intel Corporation,covering link technology;standards;SerDes architecture;electrical and optical signaling and interconnects;silicon photonics integration;optical FPGA(OFPGAs