Streamlining CXL Adoption for Hyperscale Efficiency.pdf

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1、Streamlining CXL Adoption for Hyperscale EfficiencyNilesh Shah,VP Business Development,ZeroPoint TechnologiesStreamlining CXL Adoption for Hyperscale EfficiencySustainable Scalable Computational InfrastructureSERVERChallenge4.6%3%Hyperscalers spending significant$on software based compressionCPU cyc

2、les used for compressionHyperscaler requirement:Hardware Compression is a MUST-haveDeploy New Tiers:Ordinary+Compressed DRAM memory on CXLOpportunity|Add Compressed CXL Memory TierRemoves barriers,enables diversity of Hyperscalers+Enterprise CustomersCXL ControllerBenefitSpec ComponentReduction in t

3、otal cost of ownershipStandardization,Hardware accelerated,Lossless Compressed Memory Tier Energy Efficiency,SustainabilityTransparent Hardware accelerated Compression Preserve Software InvestmentsSupport for legacy Compression Algorithms 123CXL ControllerPreserving Software Investment,without compr

4、omising performance Support for Legacy Compression AlgorithmsFuture Proof,supports Algorithm InnovationStringent Latency&Bandwidth SpecificationsRequirement:Hyperscale CXL Tiered Memory Expander SpecLegacyRoom for InnovationCompression AlgorithmsStringent RequirementsParameterSpecificationLatency Un

5、compressed Access90 to 150nsLatency Compressed Access250ns to 1usBandwidth EfficiencyRead only/Write only 80%/75%https:/www.opencompute.org/documents/hyperscale-cxl-tiered-memory-expander-for-ocp-base-specification-1-pdfCXL ControllerProposed Solution:CXL Controller with integrated Hardware Accelera

6、tionOS/HWApplicationFWCPUCompression/DecompressionCXL interfaceHostCXL.ioCXL.memMemory subsystemMediaConfigurationDynamically AdustingCompressed TierUncompressed TierCXL Type 3 Device Address SpaceCXL ControllerSolution|Portable,Integrated IPSpec compliant Plu