14-d3s3-1-Synopsys_ASIP Designer_RISC-V Summit_毛海雪_final_to_RISC-V_summit.pdf

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1、Optimize Your Own RISC-V Architecture,Using Application-Specific Processor Design Tools:Synopsys ASIP Designer毛海雪,新思科技解决方案事业部，资深应用工程师August 25,2023 2023 Synopsys,Inc.2RISC-V Extensibility ISA customization and extensibility are drivers for the growing adoption of RISC-V This results in ASIPs with a

2、RISC-V baseline ISA Preserve RISC-V compatibility Execute SW code and libraries Reuse HW peripherals Challenges Which extensions are best for the target application domain?How to obtain a high-quality SW Development Kit(SDK),including an optimizing compiler?How to obtain a reliable RTL implementatio

3、n with excellent PPA?How to verify the design?Designed for general-purpose RISC-V 2023 Synopsys,Inc.3start trv32p5x;opn trv32p5x(bit32_ifmt|bit16_ifmt);opn bit32_ifmt(majOP|majOP_IMM|majLOAD|.|majCUSTOM3);opn majOP(alu_rrr_ar_instr|mpy_rrr_instr|div_instr);opn alu_rrr_ar_instr(op:majOP_fn10,rd:eX,rs

4、1:eX,rs2:eX)action stage ID:pidX1=r1=Xrs1;pidX2=r2=Xrs2;stage EX:aluA=pidX1;aluB=pidX2;switch(op)case add:aluR=add(aluA,aluB)alu;case sub:aluR=sub(aluA,aluB)alu;case slt:aluR=slt(aluA,aluB)alu;case sltu:aluR=sltu(aluA,aluB)alu;case xor:aluR=bxor(aluA,aluB)alu;.case sra:aluR=sra(aluA,aluB)alu;stage E

5、X:pexX1=texX1=aluR;stage ME:pmeX1=tmeX1=pexX1;stage WB:if(rd:x0)w1_dead=w1=pmeX1;else Xrd=w1=pmeX1;syntax:neg rd,rs2 op rs1|snez rd,rs2 op rs1|sltz rd,rs1 op rs2|sgtz rd,rs2 op rs1|op rd,rs1,PADOP2 rs2;image :op9.3:rs2:rs1:op2.0:rd,class(alu_rrr);.ASIP Designer Industry-leading tool to design your o

6、wn Application-Specific Instruction-set Processor(ASIP)Language-based description of ISA and microarchitecture:nML Single processor model ensures that SDK and RTL are in sync Architectural exploration with Compiler-in-the-Loop&Synthesis-in-the-Loop Licensed as a tool(not IP):product differentiation,