20230614_A-103_Lockwood.PDF

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1、Session A-103:Network Acceleration 2 Removing the Tail from SmartNIC LatencyJohn W.Lockwood,CEO:Algo-Logic Systems,IncWednesday,June 14,20234:20pm Perspectives Tail Latency is a root of evil in Networks It delays application response timeWhen will this program complete?It adds uncertainly to transac

2、tionsHas it completed yet?It gets worse with more software Layers on layers 2 0.00%0.10%0.20%0.30%0.40%0.50%0.60%0.70%38.039.040.041.042.043.044.045.046.047.048.0Percentage of Packets Observed%Latency Distribution sSocket Implementation Latency Distribution with One OCSM/PacketSocketsIntel i7 Averag

3、e:41.54sTail LatencyMean LatencyRead Latency of a Key Value Store implemented in Software on a CPUMultiple Sources Latency in Software-based NICsPCIe Bus Scheduling DMA Scatter/Gather DRAM Refresh Operating System SchedulerSoftware Libraries CPU Cache Miss3 2023 Algo-Logic Systems Inc.,All rights re

4、served.4Ultra Low Latency Applications run well on FPGA SmartNICsTick-to-TradeProprietary Traders demand sub-microsecond latencyEquities,Futures,and Options trade using UDP/IP and TCP/IPHigh Frequency Trading systems source 70%of orders on modern exchanges Pre-Trade Risk ChecksVerify Compliance as o

5、rders flow through networkRequires full-stack processing with sub-microsecond LatencyReal-Time Data ProcessingReal-time sensors and actuators need deterministic response timesKey Value Store(KVS)provides associative Lookup in FPGA hardwareEntangled Applications 4 2023 Algo-Logic Systems Inc.,All rig

6、hts reserved.5Ultra Low Latency(ULL)Framework for FPGA SmartNICs Algo-Logic IP cores ULL MAC UDP Offload TCP Stack Registers for API FPGA Vendor Hardware Software Drivers PCIe/CXL Interface to SERDES Customer Software Business Logic Coded in Verilog or with High Level Synthesis(HLS)2023 Algo-Logic S